Semiconductor device having improved bias dependability and method of fabricating same

ABSTRACT

On a semiconductor substrate is formed an insulating layer having a gate insulating region, which is coated with a first polysilicon layer having a first portion and a second portion which contacts the gate insulating region. The first portion of the first polysilicon layer is then doped with an impurity such as phosphorous. The first polysilicon layer is coated with a second insulating layer on which is formed a second polysilicon layer. A first selective etching process is provided so that a capacitive insulating layer and an upper polysilicon electrode are successively formed on the first portion of the first polysilicon layer and the second portion of the first polysilicon layer is exposed. A second selective etching process is performed so that the first and second portions of the first polysilicon layer define a lower polysilicon electrode and a gate electrode, respectively. As a result, there is produced a semiconductor device having a lower polysilicon electrode doped with an impurity of conductivity type identical to conductivity type of the polysilicon gate electrode.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to semiconductor devices,and more specifically to an analog semiconductor devices having upperand lower polysilicon electrodes and a method of fabricating thesemiconductor device.

[0003] 2. Description of the Related Art

[0004] Analog metal-oxide-semiconductor transistors are composed of agate formed on an oxide layer, and a source and a drain each beingformed of upper and lower polysilicon electrodes and a capacitiveelement sandwiched therebetween. This capacitive element is requiredthat a deviation from the specified capacitance value must be maintainedin as small a range as possible under varying operating voltages. Thelower polysilicon electrode and the gate are usually fabricatedsimultaneously. However, in the prior art transistor, the lowerpolysilicon electrode has no sufficient level of impurity dose toprovide desired bias dependability. Thus there is a need to improve thebias dependability of a semiconductor device.

SUMMARY OF THE INVENTION

[0005] It is therefore an object of the present invention to provide asemiconductor device with a lower polysilicon electrode having animpurity dose that is sufficient to obtain desired bias dependabilityand a method of fabricating the semiconductor device.

[0006] According to one aspect of the present invention, there isprovided a semiconductor device comprising a semiconductor substrate, aninsulating layer on the substrate, the insulating layer having a gateinsulating region, a lower polysilicon electrode on the insulatinglayer, a capacitive insulating layer on the lower polysilicon electrode,an upper polysilicon electrode on the capacitive insulating layer, and apolysilicon gate electrode on the gate insulating region, the gateelectrode being of equal thickness to the lower polysilicon electrode.The lower polysilicon electrode is doped with an impurity ofconductivity type identical to conductivity type of the polysilicon gateelectrode.

[0007] According to a further aspect, the present invention provides amethod of fabricating a semiconductor device, comprising the steps of(a) forming a first insulating layer with a gate insulating region on asemiconductor substrate, (b) forming a first polysilicon layer on thefirst insulating layer and the gate insulating region, the firstpolysilicon layer having a first portion spaced from a second portionwhich contacts the gate insulating region, (c) doping an impurity intothe first portion of the first polysilicon layer, the impurity having aconductivity type equal to conductivity type of the first polysilicon,(d) forming a second insulating layer on the first polysilicon layer,(e) forming a second polysilicon layer on the second insulating layer,(f) performing a first selective etching process so that a capacitiveinsulating layer and an upper polysilicon electrode are successivelyformed on the first portion of the first polysilicon layer and thesecond portion of the first polysilicon layer is exposed, and (g)performing a second selective etching process so that the first andsecond portions of the first polysilicon layer define a lowerpolysilicon electrode and a gate electrode, respectively.

BRIEF DESCRIPTION OF THE DRAWIGNS

[0008] The present invention will be described in detail further withreference to the following drawings, in which:

[0009] FIGS. 1 to 8 are cross-sectional views of a semiconductor de viceof successive stages of the fabrication process of the presentinvention, wherein FIG. 1 illustrates the formation of a firstinsulating layer and a gate insulation layer on a semiconductorsubstrate and the deposition of a first polysilicon layer on the device,FIG. 2 illustrates a first impurity doping process on a selected portionof the first polysilicon layer;

[0010]FIG. 3 illustrates the deposition of a second insulating layer onthe first polysilicon layer;

[0011]FIG. 4 illustrates the deposition of a second polysilicon layerand a second impurity doping process on the second polysilicon layer;

[0012]FIGS. 5 and 6 illustrate a first etching process on a selectedportion of the second polysilicon layer and the underlying secondinsulating layer; and

[0013]FIGS. 7 and 8 illustrate a second etching process.

DETAILED DESCRIPTION

[0014] Referring to FIGS. 1 to 8, a fabrication process of asemiconductor device according to the present invention is illustrated.

[0015] In FIG. 1, a field oxide layer 2 is formed on a semiconductorsubstrate 1 as a device separator to a thickness of 200 to 500nanometers. After forming a gate oxide layer 3, the device is coatedwith a polysilicon layer 4 with a thickness of 100 to 250 nanometers. Alower electrode and a gate will be formed from this polysilicon layer.

[0016] In FIG. 2, photoresist 5 is used to provide ion implantation ofphosphorous, whereby a polysilicon region selected for the lowerelectrode is doped with the impurity of the same conductivity type asthe conductivity type of a polysilicon region to be selected as a gateelectrode on the gate oxide layer 3. If these polysilicon regions are ofthe N-type conductivity, the doping is continued until an impurity doseof 1×10¹⁵/cm³ to 1×10¹⁶/cm³ is attained. A highly doped polysiliconregion 7 is thus formed. Note that phosphorous is of the sameconductivity type as the conductivity type of a region above the gateoxide layer 3.

[0017] After removing the photoresist 5, an oxide layer 8 is formed onthe device to a thickness of 20 to 50 nanometers, as shown in FIG. 3.

[0018] In FIG. 4, a polysilicon layer 14 of thickness 100 to 200nanometers is grown on the oxide layer 8 and the polysilicon layer 14 isthen doped with phosphorous in an ion implantation process. If thepolysilicon layer 14 is of the N-type conductivity, the doping iscontinued until an impurity dose of 1×10¹⁵ /cm³ to 1×10¹⁶/cm³ isreached.

[0019] In FIG. 5, the polysilicon layer 14 and oxide layer 8 areselectively etched by using a photoresist 15. As a result, a capacitiveoxide layer 18 is formed on the highly doped polysilicon region 7 and adoped polysilicon layer 24 on the capacitive layer 18, as shown in FIG.6.

[0020] In FIG. 7, the polysilicon layer 4 is selectively etched by usingphotoresists 25 and 26 so that the lower polysilicon electrode 10 andthe gate 11 are formed as shown in FIG. 8.

[0021] The bias dependability of the transistor of this invention isimproved to 0.01%/volts to 0.03%/volts, as opposed to the dependabilityvalue of 0.3%/volts to 0.5%/volts of the prior art transistor in whichthe lower polysilicon electrode is not ion-injected with phosphorous.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; an insulating layer on said substrate, saidinsulating layer having a gate insulating region; a lower polysiliconelectrode on said insulating layer; a capacitive insulating layer onsaid lower polysilicon electrode; an upper polysilicon electrode on saidcapacitive insulating layer; and a polysilicon gate electrode on saidgate insulating region, the gate electrode and said lower polysiliconelectrode having equal thickness, said lower polysilicon electrode beingdoped with an impurity of conductivity type identical to conductivitytype of said polysilicon gate electrode.
 2. The semiconductor device ofclaim 1, wherein said lower polysilicon electrode has a larger area thansaid upper polysilicon electrode.
 3. The semiconductor device of claim1, wherein said upper polysilicon electrode is doped with an impurity ofconductivity type identical to conductivity type of said upperpolysilicon electrode.
 4. The semiconductor device of claim 1, whereinsaid lower and upper polysilicon electrodes are doped with equalimpurity dose.
 5. The semiconductor device of claim 3, wherein saidimpurity dose is 1×10¹⁵/cm³ to 1×10¹⁶/cm³.
 6. The semiconductor deviceof claim 1, wherein said capacitive insulating layer has a thickness of20 to 50 nanometers.
 7. The semiconductor device of claim 1, whereinsaid lower polysilicon electrode has a thickness of 100 to 250nanometers and said upper polysilicon electrode has a thickness of 100to 200 nanometers.
 8. A method of fabricating a semiconductor device,comprising the steps of: a) forming a first insulating layer with a gateinsulating region on a semiconductor substrate; b) forming a firstpolysilicon layer on said first insulating layer and said gateinsulating region, said first polysilicon layer having a first portionspaced from a second portion which contacts said gate insulating region;c) doping an impurity into said first portion of said first polysiliconlayer, said impurity having a conductivity type equal to conductivitytype of said first polysilicon; d) forming a second insulating layer onsaid first polysilicon layer; e) forming a second polysilicon layer onsaid second insulating layer; f) performing a first selective etchingprocess so that a capacitive insulating layer and an upper polysiliconelectrode are successively formed on said first portion of the firstpolysilicon layer, and said second portion of the first polysiliconlayer is exposed; and g) performing a second selective etching processso that said first and second portions of the first polysilicon layerdefine a lower polysilicon electrode and a gate electrode, respectively.9. The method of claim 8, further comprising the step of doping saidsecond polysilicon layer with an impurity of conductivity type identicalto conductivity type of the second polysilicon layer.
 10. The method ofclaim 8, wherein step (b) is continued until said first polysiliconlayer attains a thickness of 100 to 250 nanometers, and step (e) iscontinued until said second polysilicon layer attains a thickness of 100to 200 nanometers.
 11. The method of claim 8, wherein step (c) iscontinued until said first polysilicon layer attains an impurity dose of1×10¹⁵/cm³ to 1×10¹⁶/cm³.
 12. The method of claim 9, wherein said secondpolysilicon layer is doped until an impurity dose of 1×10¹⁵/cm² to1×10¹⁶/cm² is attained.
 13. The method of claim 8, wherein step (d) iscontinued until said second insulating layer attains a thickness of 20to 50 nanometers.